It works!
Press ENTER to continue.. Press ENTER to continue.. ____ _ ____ ____ | _ \(_) ___ ___/ ___| ___ / ___| | |_) | |/ __/ _ \___ \ / _ \| | | __/| | (_| (_) |__) | (_) | |___ |_| |_|\___\___/____/ \___/ \____| SPI State: LATENCY 8 DDR OFF QSPI OFF CRM OFF Select an action: [1] Read SPI Flash ID [2] Read SPI Config Regs [3] Switch to default mode [4] Switch to Dual I/O mode [5] Switch to Quad I/O mode [6] Switch to Quad DDR mode [7] Toggle continuous read mode [9] Run simplistic benchmark [0] Benchmark all configs Command> 9 Cycles: 0x00f3d36d Instns: 0x0003df2d Chksum: 0x5b8eb866
In the first part I got my reverse-engineered Lattice iCE40-HX8K FPGA using the completely free Project IceStorm toolchain working. I wrote a simple Verilog demo which flashed the LEDs.
Today I played with Clifford Wolf’s PicoRV32 core. What he’s written is actually a lot more sophisticated than I initially realized. There’s a simple memory mapped serial port, a memory mapped SPI bus, & a bit of interactive firmware so you can test it out (see above).
Rather than using Clifford’s build scripts (which compile the riscv32 cross-compiler and run sudo
at various points) I wrote a Makefile to build and program the FPGA on Fedora.
And it works (see above)! Now what we need is a simple 32 bit operating system that could run on it. swapforth seems to be one but as far as I can tell it hasn’t been ported to RV32. Maybe I could port Jonesforth …