It’s now possible to get a very small 32 bit RISC-V processor onto the reverse-engineered Lattice iCE40-HX8K FPGA using the completely free Project IceStorm toolchain. That’s what I’ll be looking at in this series of two articles.
I bought my development board from DigiKey for a very reasonable £41.81 (including tax and next day delivery). It comes with everything you need. This FPGA is very low-end [datasheet (PDF)], containing just 7680 LUTs, but it does have 128 kbits of static RAM, and the board has an oscillator+PLL that can generate 2-12 MHz, a few LEDs and a bunch of GPIO pins. The board is programmed over USB with the supplied cable. The important thing is the bitstream format and the probable chip layout have been reverse-engineered by Clifford Wolf and others. All the software to drive this board is available in Fedora:
dnf install icestorm arachne-pnr yosys emacs-verilog-mode
My first job was to write the equivalent of a “hello, world” program — flash the 8 LEDs in sequence. This is a good test because it makes sure that I’ve got all the tools installed and working and the Verilog program is not too complicated.
// -*- verilog -*- // Flash the LEDs in sequence on the Lattice iCE40-HX8K. module flash (input clk, output reg [7:0] leds); // Counter which counts upwards continually (wrapping around). // We don't bother to initialize it because the initial value // doesn't matter. reg [18:0] counter; // This register counts from 0-7, incrementing when the // counter is 0. The output is wired to the LEDs. reg [2:0] led_select; always @(posedge clk) begin counter <= counter + 1; if (counter[18:0] == 0) begin led_select <= led_select + 1; end end // Finally wire each LED so it signals the value of the led_select // register. genvar i; for (i = 0; i < 8; i=i+1) begin assign leds[i] = i == led_select; end endmodule // flash
It looks like the base clock frequency is 2 MHz.
The fully working example is in this repo: https://github.com/rwmjones/icestorm-flash-leds
In part 2 I’ll try to get PicoRV32 on this board.