Tag Archives: risc-v

Playing with PicoRV32 on the iCE40-HX8K FPGA Breakout Board (part 1)

It’s now possible to get a very small 32 bit RISC-V processor onto the reverse-engineered Lattice iCE40-HX8K FPGA using the completely free Project IceStorm toolchain. That’s what I’ll be looking at in this series of two articles.

I bought my development board from DigiKey for a very reasonable £41.81 (including tax and next day delivery). It comes with everything you need. This FPGA is very low-end [datasheet (PDF)], containing just 7680 LUTs, but it does have 128 kbits of static RAM, and the board has an oscillator+PLL that can generate 2-12 MHz, a few LEDs and a bunch of GPIO pins. The board is programmed over USB with the supplied cable. The important thing is the bitstream format and the probable chip layout have been reverse-engineered by Clifford Wolf and others. All the software to drive this board is available in Fedora:

dnf install icestorm arachne-pnr yosys emacs-verilog-mode

My first job was to write the equivalent of a “hello, world” program — flash the 8 LEDs in sequence. This is a good test because it makes sure that I’ve got all the tools installed and working and the Verilog program is not too complicated.

// -*- verilog -*-
// Flash the LEDs in sequence on the Lattice iCE40-HX8K.

module flash (input clk, output reg [7:0] leds);
   // Counter which counts upwards continually (wrapping around).
   // We don't bother to initialize it because the initial value
   // doesn't matter.
   reg [18:0] counter;
   // This register counts from 0-7, incrementing when the
   // counter is 0.  The output is wired to the LEDs.
   reg [2:0] led_select;

   always @(posedge clk) begin
      counter <= counter + 1;

      if (counter[18:0] == 0) begin
         led_select <= led_select + 1;

   // Finally wire each LED so it signals the value of the led_select
   // register.
   genvar i;
   for (i = 0; i < 8; i=i+1) begin
      assign leds[i] = i == led_select;      
endmodule // flash

It looks like the base clock frequency is 2 MHz.

The fully working example is in this repo: https://github.com/rwmjones/icestorm-flash-leds

In part 2 I’ll try to get PicoRV32 on this board.


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Part 1 of my article on RISC-V on LWN


I think part 2 will be next week.

LWN is a great publication, everyone should support it by subscribing.


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Fedora/RISC-V: ssh and dnf working


$ ssh -p 10000 root@localhost
root@localhost's password: riscv
[root@stage4 ~]# uname -a
Linux stage4 4.15.0-rc9-00064-gf923ce3a29af #1 SMP Thu Feb 15 10:59:13 GMT 2018 riscv64 riscv64 riscv64 GNU/Linux
[root@stage4 ~]# dnf install glibc-devel
Last metadata expiration check: 0:03:38 ago on Wed 21 Feb 2018 15:24:07 UTC.
Dependencies resolved.
 Package                  Arch          Version               Repository   Size
 glibc-devel              riscv64       2.27-4.fc28           local       1.0 M
Installing dependencies:
 glibc-headers            riscv64       2.27-4.fc28           local       442 k
 kernel-headers           noarch        4.15.0-1.fc27         local       1.1 M
 libpkgconf               riscv64       1.4.1-1.fc27          local        74 k
 libxcrypt-devel          riscv64       4.0.0-4.fc28          local        15 k
 pkgconf                  riscv64       1.4.1-1.fc27          local        35 k
 pkgconf-m4               noarch        1.4.1-1.fc27          local        15 k
 pkgconf-pkg-config       riscv64       1.4.1-1.fc27          local        14 k

Transaction Summary
Install  8 Packages

Total download size: 2.6 M
Installed size: 7.4 M
Is this ok [y/N]: 

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Fedora/RISC-V: Runnable stage 4 disk images

We’ve now got:

  1. An autobuilder.
  2. A multithreaded QEMU.
  3. A Fedora RPMs repository.
  4. A bootable disk image.

It’s unpolished and minimal at the moment, but what you can do today (if you have a Fedora 27+ x86_64 host):

  1. Enable the rjones/riscv copr and install riscv-qemu.
  2. Download the stage4-disk.img, and bbl and uncompress the disk image.
  3. Run this command:
    qemu-system-riscv64 \
        -nographic -machine virt -m 2G -smp 4 \
        -kernel bbl \
        -append "console=ttyS0 ro root=/dev/vda init=/init" \
        -device virtio-blk-device,drive=hd0 \
        -drive file=stage4-disk.img,format=raw,id=hd0 \
        -device virtio-net-device,netdev=usernet \
        -netdev user,id=usernet
  4. Inside the guest drop a repo file into /etc/yum.repos.d containing:
  5. Use tdnf --releasever 27 install ... to install more packages.


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Fedora/RISC-V: the final bootstrap

There are bootable (but very minimal) disk images built cleanly from RPMs: https://fedorapeople.org/groups/risc-v/disk-images/

More soon …

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RISC-V Tokyo

Today (was) RISC-V Day 2017 Tokyo at the University of Tokyo (programme in English, more information in English). My colleague Wei Fu gave a talk on the status of Fedora on RISC-V. I hope it was recorded somewhere. If it appears online I’ll update this post.

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Fabrice Bellard’s RISCVEMU supports Fedora/RISC-V

You can now boot Fedora 25 for RISC-V in Fabrice Bellard’s RISCVEMU RISC-V emulator. Here’s how in four simple steps:

  1. Download riscvemu-XXX.tar.gz and diskimage-linux-riscv64-XXX.tar.gz from Fabrice’s site.
  2. Download the latest stage 4 disk image for Fedora/RISC-V from here.
  3. Compile riscvemu. You should just need to do make.
  4. Run everything like this:
    ./riscvemu -b 64 ../diskimage-linux-riscv64-XXX/bbl.bin stage4-disk.img

If you’re going to do serious work inside the disk image then you’ll probably want to customize it with extra packages. See these instructions.

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