Tag Archives: risc-v

My talk from the RISC-V workshop in Barcelona

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“RISCY BUSINESS” runs Fedora in a chroot on HiFive Unleashed

Note you can now run Fedora directly, see the instructions here:

https://fedorapeople.org/groups/risc-v/disk-images/hifive-unleased/

https://github.com/rwmjones/fedora-riscv-kernel/tree/sifive_u540

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RISC-V 8th Workshop Agenda

The RISC-V 8th Workshop is happening in Barcelona next month and the agenda and speakers have been announced:

https://tmt.knect365.com/risc-v-workshop-barcelona/agenda/2

David Abdurachmanov and myself are giving a short talk about Fedora on RISC-V at 4pm on Tuesday 8th May.

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HiFive Unleashed for Fedora

I’m not even taking this precious cargo out of its static bag until I’ve got everything else ready …

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Fedora/RISC-V running on the HiFive Unleashed board

Thanks to David Abdurachmanov and SiFive for these pictures.

HiFive Unleashed Freedom U540 and their crowd-funding page.

Fedora/RISC-V and our downloadable and now bootable disk images.

Previously …

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Part 2: LWN article on Fedora/RISC-V

https://lwn.net/SubscriberLink/749443/3b74c2ae8d2e11b9/

Part 1 was here: https://lwn.net/Articles/749185/

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Playing with PicoRV32 on the iCE40-HX8K FPGA Breakout Board (part 2)

It works!

Press ENTER to continue..
Press ENTER to continue..

  ____  _          ____         ____
 |  _ \(_) ___ ___/ ___|  ___  / ___|
 | |_) | |/ __/ _ \___ \ / _ \| |
 |  __/| | (_| (_) |__) | (_) | |___
 |_|   |_|\___\___/____/ \___/ \____|


SPI State:
  LATENCY 8
  DDR OFF
  QSPI OFF
  CRM OFF
Select an action:

   [1] Read SPI Flash ID
   [2] Read SPI Config Regs
   [3] Switch to default mode
   [4] Switch to Dual I/O mode
   [5] Switch to Quad I/O mode
   [6] Switch to Quad DDR mode
   [7] Toggle continuous read mode
   [9] Run simplistic benchmark
   [0] Benchmark all configs

Command> 9
Cycles: 0x00f3d36d
Instns: 0x0003df2d
Chksum: 0x5b8eb866

In the first part I got my reverse-engineered Lattice iCE40-HX8K FPGA using the completely free Project IceStorm toolchain working. I wrote a simple Verilog demo which flashed the LEDs.

Today I played with Clifford Wolf’s PicoRV32 core. What he’s written is actually a lot more sophisticated than I initially realized. There’s a simple memory mapped serial port, a memory mapped SPI bus, & a bit of interactive firmware so you can test it out (see above).

Rather than using Clifford’s build scripts (which compile the riscv32 cross-compiler and run sudo at various points) I wrote a Makefile to build and program the FPGA on Fedora.

And it works (see above)! Now what we need is a simple 32 bit operating system that could run on it. swapforth seems to be one but as far as I can tell it hasn’t been ported to RV32. Maybe I could port Jonesforth …

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