Part 1 of my article on RISC-V on LWN

https://lwn.net/SubscriberLink/749185/61734f481b2cad8d/

I think part 2 will be next week.

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4 Comments

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4 responses to “Part 1 of my article on RISC-V on LWN

  1. These “cores” (code that compiles to Verilog) — what languages are they written in and is there a higher level language for modelling these things? Should we invent one? I saw some scala, C, and other things. I’m trying to understand the tool chain along with what’s missing till I can get from `git` to hardware. I would imagine intel has a bunch of proprietary things that make all of this more powerful and optimized.

    Suppose I download one of the “cores” projects and edit it slightly, how difficult/expensive is it to take my new version and get a chip made?

    I realize that I’d need other (currently proprietary bits) as well.

    Thanks!

    • rich

      It’s written in Chisel which is indeed a DSL embedded in Scala. Unfortunately the situation for getting from Chisel to something you can try in an FPGA involves a lot of proprietary software, namely Xilinx’s awful Vivado software (and by “a lot”, I really mean “a lot” — it’s a 40 GB download). There used to be a Chisel to C++ converter (for emulating your design) but I believe it has been dropped. The advantage of Chisel is that it’s nicely parameterized, so with only a few changes you can change (eg) 1 to 2 cores or change the cache set associativity.

      Alternately you can use the completely free IceStorm toolchain, and you can just about get the smallest variant of PicoRV32 on to the largest supported IceStorm FPGA (which has only 8K LUTs). However that won’t let you experiment with Chisel because the PicoRV32 is written in Verilog directly. (Edit: I’m intending to do a future article about PicoRV32 and IceStorm. Already bought the hardware, it’s sitting in its box waiting for me to have a spare minute to play with it)

      In terms of how difficult it is to make a chip, you’re going to be looking at $100K to make a low end design (using something like TSMC’s “CyberShuttle” where many users can share the costs of a single shuttle). To — well — how much do you want to spend? Anything from $100m to $1bn for the most extremely high performing chips. Oh and making a chip involves the most incredible proprietary toolchains you can imagine.

      Edit: Very appropriate talk: https://www.youtube.com/watch?v=pxd93jb1OAk

  2. Laszlo Ersek

    great article, looking forward to part 2 🙂

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