There are various open source ISAs and chip designs. I’ve previously run OpenRISC 1200 on an FPGA. Another effort is the RISC-V (“RISC Five”) project, which is developing an open, patent-free 64 bit ISA. It has a sister project lowRISC which aims to produce a synthesizable RISC-V FPGA design “in 6 months”, and tape out by the end of this year (I’m a little skeptical of the timeframes).
RISC-V has added support to a fork of qemu:
$ git remote add riscv https://github.com/riscv/riscv-qemu $ git fetch riscv $ git checkout -b riscv-master --track riscv/master $ ./configure --target-list="riscv-softmmu" $ make $ ./riscv-softmmu/qemu-system-riscv -cpu \? RISCV 'riscv-generic' $ ./riscv-softmmu/qemu-system-riscv -machine \? Supported machines are: board RISCV Board (default) none empty machine
To save yourself a world of pain, download a RISC-V Linux kernel binary and root image from here.
$ file ~/vmlinux /home/rjones/vmlinux: ELF 64-bit LSB executable, UCB RISC-V, version 1 (SYSV), statically linked, BuildID[sha1]=d0a6d680362018e0f3b9208a7ea7f79b2b403f7c, not stripped
Then you can boot the image in the usual way:
$ ./riscv-softmmu/qemu-system-riscv \ -display none \ -kernel ~/vmlinux \ -hda ~/root.bin \ -serial stdio
The root filesystem is very sparse:
# uname -a Linux ucbvax 3.14.15-g4073e84-dirty #4 Sun Jan 11 07:17:06 PST 2015 riscv GNU/Linux # ls /bin ash chgrp dd ln mv rmdir touch base64 chmod df ls nice sleep true busybox chown echo mkdir printenv stat uname cat cp false mknod pwd stty usleep catv date fsync mount rm sync # ls /sbin init # ls /usr/bin [ dirname groups mkfifo sha1sum tac uniq [[ dos2unix head nohup sha256sum tail unix2dos basename du hostid od sha3sum tee uudecode cal env id printf sha512sum test uuencode cksum expand install readlink sort tr wc comm expr logname realpath split tty whoami cut fold md5sum seq sum unexpand yes
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