HiFive Unmatched

“RISCY BUSINESS” runs Fedora in a chroot on HiFive Unleashed

Note you can now run Fedora directly, see the instructions here:

https://fedorapeople.org/groups/risc-v/disk-images/hifive-unleased/

https://github.com/rwmjones/fedora-riscv-kernel/tree/sifive_u540

HiFive Unleashed cpuinfo and dmesg

hart	: 1
isa	: rv64imafdc
mmu	: sv39
uarch	: sifive,rocket0

hart	: 2
isa	: rv64imafdc
mmu	: sv39
uarch	: sifive,rocket0

hart	: 3
isa	: rv64imafdc
mmu	: sv39
uarch	: sifive,rocket0

hart	: 4
isa	: rv64imafdc
mmu	: sv39
uarch	: sifive,rocket0

Kernel boot messages after the fold.

HiFive Unleashed booting

HiFive Unleashed for Fedora

I’m not even taking this precious cargo out of its static bag until I’ve got everything else ready …

Fedora/RISC-V running on the HiFive Unleashed board

Thanks to David Abdurachmanov and SiFive for these pictures.

HiFive Unleashed Freedom U540 and their crowd-funding page.

Fedora/RISC-V and our downloadable and now bootable disk images.

Previously …

RISC-V on an FPGA, pt. 8

Some thoughts on SiFive Freedom U500 on the low-end Arty Board:

• 256MB (249MB available), vs 128MB for the Nexys 4. However memory is used for the filesystem initramfs / tmpfs (see next point) so there is a trade-off between RAM and storage. Recall the Nexys 4 has a microSD card for storage.
• The root filesystem is the initramfs, presumably loaded off the 16MB of SPI flash included with the board. So it’s more like an embedded target than something you could do any development on.
• Slow – noticeably slower than lowRISC on the Nexys 4. However it’s also under half the price, and this is an FPGA design, and the performance of the real hardware will be completely different.
• I was kind of expecting that ethernet would work, but in any case it doesn’t appear to work for me.
• You can replace their Linux kernel and root image with your own — see section 5 in the documentation. However that step, as well as programming the board, requires the proprietary Vivado software. AFAICT there is no free software alternative.

RISC-V on an FPGA, pt. 7

Today I’m going to try SiFive’s Freedom U500 64 bit RISC-V design on the very low-end $148 Arty Board. If you want more background into what SiFive are up to then I recommend watching this 15 minute video, but in brief they seem to be positioning themselves as a distributor and integrator of RISC-V.

The good thing is they compile everything you need including the Xilinx bitstream. The bad thing is that these are behind a registration wall with a poisonous license agreement (in particular, non-commercial use only). I hope this is only because of the bits of 3rd party proprietary IP they are using for ethernet, flash, UART, etc.

If you want to do this yourself, read the getting started guide here. Assuming you have Xilinx Vivado installed, following the instructions is completely straightforward except for one point: You need to do “Boot from Configuration Memory device” after programming. Anyway you will have a booting Linux/RISC-V in a few minutes.

After the cut, the boot output.