RISC-V on an FPGA, pt. 8

Some thoughts on SiFive Freedom U500 on the low-end Arty Board:

  • 256MB (249MB available), vs 128MB for the Nexys 4. However memory is used for the filesystem initramfs / tmpfs (see next point) so there is a trade-off between RAM and storage. Recall the Nexys 4 has a microSD card for storage.
  • The root filesystem is the initramfs, presumably loaded off the 16MB of SPI flash included with the board. So it’s more like an embedded target than something you could do any development on.
  • Slow – noticeably slower than lowRISC on the Nexys 4. However it’s also under half the price, and this is an FPGA design, and the performance of the real hardware will be completely different.
  • I was kind of expecting that ethernet would work, but in any case it doesn’t appear to work for me.
  • You can replace their Linux kernel and root image with your own — see section 5 in the documentation. However that step, as well as programming the board, requires the proprietary Vivado software. AFAICT there is no free software alternative.


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2 responses to “RISC-V on an FPGA, pt. 8

  1. problemchild68

    Really pleased you have obviously become so excited with the world of FPGA CPUs and of course implementing Linux on them :).
    Unfortunately I think we are all frustrated with the state of propreitary Tools and the IP for key components such as Video and other I/O. have you looked at bodging in some components from opencores.org or some such?

    BTW there is some work on opensource tools to produce the Bitsreams for the Xilinx parts but I’m not certain of what parts are supported.

    Good work either way waiting for more installments in the story.

    p.s. do you know of any work to support an Accelerated Mali driver in say Fedora??? looking for that big style !

  2. The reverseengineering of Lattice ICE40 FPGA was done as a proove on concept. Series 7 Xilinx FPGAs could be reversed too, but there is currently just not enough interest in doing it or support someone doing it. So lets build the community until there is enough pressure to also do Xilinx reversing.

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